Conventionally, aluminum (Ai) or Al alloy has been widely used for a wiring material of semiconductor devices. However, with the progression in miniaturization and high speed operation of semiconductor devices, copper (Cu) has been used as a wiring material for an improvement in transmission delay of wiring, because copper has a lower resistivity. In addition, Cu has a melting point of 1083° C., which is higher than the melting point of Al of 660° C., and is generally considered to be high in electromigration (EM) resistance and also excellent in the aspect of reliability.
When wiring is formed of Cu, since processing by dry etching of Cu is difficult, a damascene method has been generally used for forming Cu wiring. The damascene method is a method for forming Cu wiring by forming wiring grooves in an insulating film formed on a semiconductor substrate, forming a Cu film so as to fill up the grooves, and polishing the Cu film until the insulating film is exposed so as to remove an excessive Cu film on the insulating film excluding that in the wiring grooves, whereby Cu wiring is provided in a buried manner into wiring grooves.
In addition, for using Cu as a wiring material, it is necessary to provide a barrier metal film around Cu in order to prevent Cu from diffusing into an insulating film and Cu corrosion. In the following, description will be given of a currently generally used manufacturing method of a semiconductor device having Cu wiring while referring to the drawings.
FIGS. 9(a) through (g) are sectional views showing a conventional manufacturing method for a semiconductor device. FIG. 9(a) shows lower-layer wiring on which upper-layer wiring is to be formed. This lower-layer wiring is composed of an insulating film 1a, a barrier metal film 3a, Cu 4a, and a barrier insulating film 8a. This lower-layer wiring part is also formed by use of processes similar to those of the upper-layer wiring.
As shown in FIG. 9(b), an insulating film 1b is formed on this lower-layer wiring, and then as shown in FIG. 9(c), in the insulating film, wiring grooves and wiring holes are formed by lithography and anisotropic etching. Thereafter, as shown in FIG. 9(d), a barrier metal film 3b, which is a conductive film, is formed on the internal surfaces of the wiring grooves and wiring holes, and as shown in FIG. 9(e), in a manner filling up the wiring grooves and wiring holes, a Cu film 4b is formed on the insulating film 1b. 
Next, as shown in FIG. 9(f), by CMP (Chemical Mechanical Polishing), an excessive Cu film 4b and barrier metal film 3b excluding the parts buried in the wiring grooves and wiring holes are removed. Then, as shown in FIG. 9(g), a barrier insulating film 8b, which is an isolator, is formed on the entire surface. In such a manner, a Cu wiring structure whose lower surface and side surfaces have been covered with the barrier metal film 3b, which is a conductor, and whose upper surface has been covered with the barrier insulating film 8b, which is an insulator, is formed.
However, in Japanese Published Unexamined Patent Application No. 2001-298084, there is a description that when a wiring (wiring groove) width is seven times or more a via (also referred to as a wiring hole or a contact hole) diameter, a disconnection owing to a void (cavity) which is generated under and inside the via, and the disconnection occurs at the most accelerated rate at around 150° C.
Similarly, in the following publication, there is a description that, when lower-layer wiring to which vias are connected has a wide width, there is voiding on the surface of lower-layer wiring to be a connecting portion, and the disconnection easily occurs during isothermal storage at 190° C.
“Stress-Induced Voiding Under Vias Connected TO Wide Cu Metal Leads” (Proceeding of IEEE International Reliability Physics Symposium 2002, USA, The Electron Device Society and The Reliability Society of the Institute of Electrical and Electronics Engineers, Inc, Published on Apr. 7, 2002, p 312-321)
Next, description will be given of a method for manufacturing a conventional semiconductor device shown in FIGS. 10(a) through (h). This method is a method for forming copper alloy wiring when an alloy sputter target disclosed in Japanese Published Unexamined Patent Application No. 2000-150522 and the like is used. FIG. 10(a) shows lower-layer wiring on which an upper layer is to be formed. This lower-layer wiring part is also formed by processes similar to those of the upper layer shown in the following.
First, as shown in FIG. 10(b), an insulating film 1b is formed on this lower-layer wiring. Then, as shown in FIG. 10(c), in the insulating film 1b, wiring grooves and wiring holes are formed by lithography and anisotropic etching. Then, as shown in FIG. 10(d), a barrier metal film 3b, as a conductive film is formed on the entire surface including the internal surfaces of the wiring grooves and wiring holes. Furthermore, an alloy seed layer 10b to be electrodes when filling up the wiring grooves and wiring holes is formed on the barrier metal 3b by a sputtering method using a Cu alloy target. Then, as shown in FIG. 10(e), by a plating method or a CVD method (Chemical Vapor Deposition Method), a Cu film 4b is formed on the entire surface so as to fill up the wiring grooves and wiring holes.
Next, as shown in FIG. 10(f), an additional element in the alloy seed layer 10b is diffused into the Cu film 4b by heat treatment, whereby the Cu film 4b is alloyed to form a Cu alloy film 6c. 
Next, as shown in FIG. 10(g), an excessive Cu alloy film 6c and barrier metal film 3b on the surface of the insulating film 1b excluding the parts buried in the wiring grooves and wiring holes are removed by CMP, and as shown in FIG. 10(h), a barrier insulating film 8b, which is an insulator, is formed on the entire surface. In such a manner, a Cu wiring structure whose lower surface and side surfaces have been covered with the barrier metal film 3b, which is a conductor, and whose upper surface has been covered with the barrier insulating film 8b, which is an insulator, is formed.
In addition, in Japanese Published Unexamined Patent Application No. 2000-208517, when using metal wiring of a semiconductor device, a technique using a CuSn alloy seed layer has been disclosed.
With regard to reliability of Cu wiring formed as shown in FIG. 9(a) through (g), in addition to EM resistance, void formation owing to a stress induced migration (SM) has become a crucial problem. A tensile stress caused by a difference in thermal expansion coefficients between the Cu and insulating film to be applied to a Cu wiring portion serves as a driving force of the void formation.
Correspondingly, as described in the above-described Japanese Published Unexamined Patent Application No. 2001-298084 and the above-described publication, a disconnection owing to a void formation occurs. Such a failure caused by stress is expected to become more prominent when the via diameter is further reduced by miniaturization of the element.
In addition, as countermeasures against EM and SM, priorly, alloying of Cu wiring has been investigated in numerous cases. In alloying, by changing Cu composition, migration resistance of Cu can be improved.
However, as in the above-described Japanese Published Unexamined Patent Application No. 2000-208517, Cu alloy wiring formed by the method shown in FIG. 10(a) through (h) has the following problems. Namely, when an alloy seed layer 10b was formed, by diffusing an additional element in the alloy seed layer 10b into the Cu film 4b by heat treatment, a Cu alloy is formed. On the other hand, the additional element in the alloy seed layer 10b is diffused into the Cu film 4b by heat treatment, and is partly precipitated on crystal grain boundaries 7b of the Cu alloy film 6c, however, the additional element mostly remains in crystal grains of the Cu alloy film 6c. Electron scattering occurs under the influence of this additional element remaining in crystal grains of the Cu alloy film 6c. 
In addition, under the influence of grain boundary scattering of electrons as a result of a reduction in the size of Cu crystal grains by heat treatment, resistivity of the formed Cu alloy wiring rises.
Furthermore, although it is ideal that the additional element in the alloy seed layer 10b uniformly diffuses into the Cu film 4b, if the diffusion speed of the additional element into the Cu film 4b is slow, the additional element remains in the alloy seed layer 10b in large quantity. At this time, under the influence of the additional element remaining in the alloy seed layer 10b in large quantity, resistivity of the Cu wiring rises, and also concentration profiles of the additional element in the bulk Cu film 6c can change as a result of heat treatment to form wiring of a more upper layer, therefore, instability occurs with respect to a heat cycle at the time of multi-layer formation.
Furthermore, under the influence of the additional element in the alloy seed layer 10b, growth of the crystal grains of the Cu film 6c is suppressed. Particularly, in such a case where the additional element is precipitated on Cu crystal grain boundaries, pinning of the grain boundaries occurs under the influence of the precipitated additional element, and growth of the Cu crystal grains in heat treatment is suppressed. As a result, since the diameter of Cu crystal grains is reduced, this raises resistivity of the Cu wiring and also exerts an influence on a decline in wiring reliability caused by EM and SM and the like.
In addition, when the Cu alloy seed layer 10b is formed by sputtering, since Cu filling capability by sputtering is different depending on the width of the wiring groove and wiring hole, inconvenience occurs. Namely, with narrow wiring, since sputter filling capability is deteriorated, the alloy seed layer 10b deposited on the bottom of the wiring groove has a thin film thickness. Therefore, concentration of the additional element in the Cu wire in a narrow-width wiring groove becomes relatively small compared to that of a wide-width wiring groove. As a result, the Cu wires in the narrow-width wiring groove has a low resistivity compared to that of a wide-width wiring groove. As such, when the alloy seed layer 10b is formed by a sputtering method, since concentration of the additional element is different depending on the width of the wiring groove, resistivity of the Cu wiring varies depending on the width of the wiring groove.
Furthermore, in the above-described Japanese Published Unexamined Patent Application 2000-208517, it has been reported that adhesion between the barrier metal film and the alloy seed layer is deteriorated when a CuSn alloy seed layer is used. As such, securing adhesion between the barrier metal layer 3b and alloy seed layer 10 has also become a crucial problem.
An object of the present invention is to provide a highly reliable copper alloy for wiring for which wiring delay has been improved, which is high in performance, and which is excellent in SM resistance and EM resistance, a semiconductor device using the same wiring, a method for forming the wiring, and a method for manufacturing the semiconductor device.